E.1) HWP (Intel SpeedShift Technology) CPU Power Management Configuration
On Skylake-X/X299 Systems with unlocked mainboard BIOS MSR 0xE2 BIOS register and SMBIOS iMacPro1,1 we gain fully native HWP (IntelSpeedShift) Power Management after disabling the last remaining XCPM KernelToPatch entry "xcpm_core_scope_msrs" in the config.plist under Section "Kernel and Kext Patches" of Clover Configurator, which by default is still implemented but disabled in the config.plist of my actual respective X299 EFI-Folder distribution.
Users with locked mainboard BIOS MSR 0xE2 register, still have to use the "xcpm_core_scope_msrs" XCPM KernelToPatch entry to successfully boot their systems. Otherwise the OSX Kernel will write to that BIOS register and cause KP at boot!
HWP is a way for the processor itself to manage the power consumption, with minor input from OSX on what it thinks it needs. In contrary, XCPM is the OSX power management part. It directly controls older hardware like Broadwell-E/EP or Haswell-E/EP and enables HWP on newer hardware like Skylake-X. It also sets some HWP variables, like the desired frequency at the maximum.
XCPM is enabled by default.
For it's complete configuration, XCPM still requires the CPU "plugin-type" injection to properly load the required XCPM frequency vectors from the iMacPro.plist, which can be directly achieved within the config.plist by checking "PluginType" in Section "ACPI" of Clover Configurator.
How to verify a working xcpm configuration?
a.) Typically the command "sysctl machdep.xcpm.mode" reveals 1, which means that XCPM is active.
b.) Verify that in the IORegistryExplorer you have now under CP00@0 the following entry:
Code:
Property: Type: Value:plugin-type Number 0x1
c.) Also verify with the terminal command:
Code:
kextstat|grep -y x86plat
that the "X86PlatformPlugin.kext" is now loaded. If the command returns something like
2.) /Advanced/CPU Configuration/
a.) Hyper Threading [ALL]: Enabled
b.) MSR Lock Control: Disabled
3.) /Advanced/CPU Configuration/CPU Power Management Configuration/
a.) Enhanced Intel Speed Step Technology (EIST): Disbaled
b.) Autonomous Core C-States: Enabled
c.) Enhanced Halt State (C1E): Enabled
d.) CPU C6 report: Enabled
e.) Package C-State: C6(non retention) state
f.) Intel SpeedShift Technology: Enabled (crucial for native HWP Intel SpeedShift Technology CPU Power Management)
g.) MFC Mode Override: OS Native
IA32_HWP_REQUEST................(0x774) : 0x40000FFFF07
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- Minimum Performance................. : 7
- Maximum Performance................. : 255
- Desired Performance................. : 255
- Energy Efficient Performance........ : 0
- Activity Window..................... : 0, 0
- Package Control..................... : 1 (control inputs to be derived from IA32_HWP_REQUEST_PKG)
IA32_HWP_STATUS..................(0x777) : 0x0
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- Guaranteed Performance Change....... : 0 (has not occured)
- Excursion To Minimum................ : 0 (has not occured)
CPU Ratio Info:
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Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 10 (1000 MHz)
Maximum non-Turbo Ratio/Frequency........: 24 (2400 MHz)
Maximum Turbo Ratio/Frequency............: 43 (4300 MHz)
P-State ratio * 100 = Frequency in MHz
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