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小-鸡.巴-弟弟
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Connections:
1:
2:
* 3: [DP 1.2 4 x HBR2] Status: [4 x HBR2 7777] caps [features 0x101141b, p_encoding 0xd] Sink OUI:204-045-140 27MD5K [050-055-077-068-053-075] HW Version: 48 FW Version: 3.4
4:
## Register Dump Port 3 - Start ##
000000: 0x12 0x14 0xc4 0x01 0x01 0x00 0x01 0x80 0x02 0x00 0x00 0x00 0x00 0x00 0x04 0x00
Reg: 000000: 12 : DPCD_REV: 1.2
Reg: 000001: 14 : MAX_LINK_RATE: HBR2
Reg: 000002: c4 : MAX_LANE_COUNT: 4, TPS3_SUPPORTED: 1, ENHANCED_FRAME_CAP: 1
Reg: 000003: 01 : MAX_DOWNSPREAD: 0.5% down, NO_AUX_HANDSHAKE_LINK_TRAINING: 0
Reg: 000004: 01 : NORP: 1
Reg: 000005: 00 : DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT: 0, DWN_STRM_PORT_TYPE: [0] DisplayPort, FORMAT_CONVERSION: 0, DETAILED_CAP_INFO_AVAILABLE: 0
Reg: 000006: 01 : MAIN_LINK_CHANNEL_CODING: ANSI 8B/10B
Reg: 000007: 80 : DOWN_STREAM_PORT_COUNT: DWN_STRM_PORT_COUNT: 0, MSA_TIMING_PAR_IGNORED: 0, OUI: 1
Reg: 000008: 02 : RECEIVE_PORT0_CAP_0: LOCAL_EDID_PRESENT: 1, ASSOCIATED_TO_PRECEDING_PORT: 0
Reg: 000009: 00 : RECEIVE_PORT0_CAP_1: BUFFER_SIZE: 32
Reg: 00000a: 00 : RECEIVE_PORT1_CAP_0:
Reg: 00000b: 00 : RECEIVE_PORT1_CAP_1:
Reg: 00000c: 00 : I2C Speed:
Reg: 00000d: 00 : eDP_CONFIGURATION_CAP: ALTERNATE_SCRAMBLER_RESET_CAPABLE: 0, FRAMING_CHANGE_CAPABLE: 0
Reg: 00000e: 04 : TRAINING_AUX_RD_INTERVAL: 16 ms, EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT: NO
Reg: 00000f: 00 : ADAPTER_CAP: FORCE_LOAD_SENSE_CAP: 0, ALTERNATE_I2C_PATTERN_CAP: 0
000020: 0x00 0x00 0x00
Reg: 000020: 00 : FAUX_CAP: FAUX_CAP: 0
Reg: 000021: 00 : MSTM_CAP: MST_CAP: 0
Reg: 000022: 00 : NUMBER_OF_AUDIO_ENDPOINTS: 0
000060: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Reg: 000060: 00 : DSC Support: 0
Reg: 000061: 00 : DSC Algorithm revision: 0
Reg: 000062: 00 : DSC RC Buffer Block size: 0
Reg: 000063: 00 : DSC RC Buffer size: 0
Reg: 000064: 00 : DSC slice Capabilities 1 : 0
Reg: 000065: 00 : DSC Line buffer bit depth: 0
Reg: 000066: 00 : DSC Block prediction support: 0
Reg: 000067: 00 : DSC Maximum bit per pixel: 0
Reg: 000068: 00 : DSC Maximum bit per pixel: 0
Reg: 000069: 00 : DSC Decoder color format capabilities: 0
Reg: 00006a: 00 : DSC decoder color depth capabilities: 0
Reg: 00006b: 00 : DSC Peak Throughput: 0
Reg: 00006c: 00 : DSC Maximum Slice width: 0
Reg: 00006d: 00 : DSC Slice capabilities 2: 0
Reg: 00006e: 00 : Reserved: 0
Reg: 00006f: 00 : DSC Bits per pixel increment: 0 |
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