static int sm_get_bus_speed (const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case 0x0d: // Pentium M, "Dothan", 90nm
case 0x0e: // Core Solo/Duo, "Yonah", 65nm
case 0x0f: // Pentium 4, Core 2, Xeon, "Merom", "Conroe", 65nm
case 0x17: // Core 2 Extreme, Xeon, "Penryn", "Wolfdale", 45nm
case 0x1c: // Intel Atom
case 0x27: // Intel Atom, "Lincroft", 45nm
return 0; // TODO: populate bus speed for these processors
break;
case 0x2f: // Core i7, "Westmere-Ex", 45nm, Hexa-Core
return 0; // TODO: populate bus speed for these processors
break;
case 0x0c: // Core i7 & Atom
if(strstr(Platform.CPU.BrandString, "Atom")) return 0;
case 0x19: // Core i5 650
case 0x1a: // Core i7 LGA1366, Xeon 550, 45nm
case 0x1e: // Core i7, i5 LGA1156, "Lynnfield", "Jasper", 45nm
case 0x1f: // Core i7, i5, Nehalem
case 0x25: // Core i7, i5, i3 LGA1156, "Westmere", 32nm
case 0x2a: // Sandy Bridge, 32nm
case 0x2c: // Core i7 LGA1366, "Westmere", 32nm, Hexa-Core
case 0x2e: // Core i7, Nehalem-Ex, Xeon
{
// thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus, 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus, 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;